1. Field of the Invention
The present invention generally relates to FIFO (First-In First-Out) devices having a FIFO type memory used in a data transfer control device of a PCI host card with an IEEE 1394 interface based upon an OHCI (Open Host Controller Interface) standard inside a personal computer and so on and, more particularly, to a receiving FIFO device serving to transfer data received from an external device via an IEEE 1394 type bus to the personal computer and so on via a PCI bus.
2. Description of the Related Art
In conventional data transfer control devices inside of a personal computer and so on including a serial bus interface circuit based upon the IEEE 1394, an IEEE 1394 type bus is connected with a physical layer, and the physical layer is connected with a link layer. The link layer is subsequently connected with a sending FIFO device for asynchronous packet, a sending FIFO device for isochronous packet and a receiving FIFO.
The sending FIFO device for asynchronous packet, the sending FIFO device for isochronous packet and the receiving FIFO are connected with a sending DMA (Direct Memory Access) device for asynchronous packet, a sending DMA device for isochronous packet and a receiving DMA, respectively. Then, these DMA devices are connected with a PCI control unit for controlling a PCI bus, thereby connected with a PCI bus via the PCI control unit.
Each of the above-mentioned DMA devices is connected with the PCI bus. However, these DMA devices are not mutually synchronized so that the DMA devices are likely to conflict with each other for the use of the PCI bus. Accordingly, it is highly probable that a personal computer performs poorly under the situation that the personal computer includes a plurality of IEEE 1394 type devices connected mutually. Under the situation, in order to prevent the conflict for the PCI bus as much as possible, it is necessary to avoid occupying the PCI bus for the sake of error data that should be ignored by nature.
FIG. 1 is a diagram illustrating a conventional receiving FIFO device. In FIG. 1, a receiving FIFO device 100 comprises a memory part 101, an input control part 102 for controlling an input operation of data, and an output control unit 103 for controlling an output operation of data. The memory part 101 is formed of a memory circuit in which an input packet is actually stored. Under FIG. 1, the memory part 101 possesses memory capacity of 1024×33 bits. The memory part 101 receives an input data DI[32:0] from the link layer via a data input bus 104 and a timing signal MWR from the input control part 102. The timing signal MWR serves to gain timing when the input data DI[32:0] from the input control part 102 is written in the memory part 101.
Also, the memory part 101 receives a write address ADI[9:0] from the input control part 102 and a read address ADO[9:0] from the output control part 103. The write address ADI[9:0] indicates an address in the memory part 101 in which data should be written and possesses memory capacity of 10 bits. The read address ADO[9:0] indicates an address in the memory part 101 from which data should be read and possesses memory capacity of 10 bits. An output data DO[32:0] from the memory unit 101 is sent to the receiving DMA device, which is not illustrated in FIG. 1, via a data output bus 105.
The input control part 102 receives a timing signal LWR# from the link layer and the read address ADO[9:0] from the output control part 103. The timing signal LWR# serves to gain timing when data should be written. In addition, the input control part 102 supplies to the link layer a FULL signal indicating a FULL state, that is, the memory part 101 has no room to store data. At the same time, the input control part 102 supplies to the output control part 103 an EMPTY signal indicating an EMPTY state, that is, the memory part 101 has some rooms to store data.
The output control part 103 receives a read data request signal FRREQ# from the receiving DMA device, and supplies a read data acknowledge signal FRACK# to the receiving DMA device. Here, the breadth of each data in the memory part 101 possesses memory capacity of 33 bits, because an IEEE 1394 type packet is basically formed of 32 bits and one extra bit, which is added in the link layer, serves to indicate the last data of the packet.
FIG. 2 is a block diagram illustrating a structure of the input control part 102 shown in FIG. 1. In FIG. 2, the timing signal LWR# is inverted to generate a timing signal MWR. The timing signal MWR is supplied to an enable terminal EN of a 10 bit counter 201 serving to control its internal counter. The 10 bit counter 201 sends the write address ADI[9:0] to the memory part 101. Also, the 10 bit counter 201 is set as “000h” at the reset, that is, the time when a reset signal Rs# being LOW is supplied to a reset terminal R#. A decoder 202 decodes the write address ADI[9:0] and the read address ADO[9:0] in a predetermined way to generate and send the FULL signal and the EMPTY signal.
A received IEEE 1394 type data written in the memory part 101 comprise a header part containing a type of packet and address information, a data part containing data information, and a trailer part containing receiving time and acknowledge information sent back to a sender of the received data. Under the header part, the data part and the trailer part, one word is formed of 32 bit data, which is called a quadret hereafter. The trailer part, which is the last quadret of received data, has the acknowledge information including various types of error information.
Under the above-mentioned conventional receiving FIFO device 100, a receiving packet does not prove an error packet to be canceled out of the device until the trailer part, the last portion of the packet, is received. As a result, even if the receiving FIFO device receives the error packet and then the DMA device receives the error packet, the PCI bus is occupied for the sake of the error packet. Accordingly, conventional FIFO devices has the problem that the occupation of the PCI bus for the transferring of the error packet is likely to cause a conflict for the PCI bus among the above-mentioned DMA devices thereby decreasing processing power of the entire system.